DRW is a principal trading firm, which means no outside investors or third party funds, and we trade for our own account in markets around the world. Our trading is diverse—across asset classes and instruments, using our own models and systems—and it’s this diversification that sets us apart. Founded in 1992 by bringing together technology, research, and risk management to capture trading and investment opportunities, and we still take that approach today. Though we’ve grown to more than 700 exceptional people in six cities around the world, we have the spirit of a start-up and a constant focus on results.
We are currently seeking a Senior FPGA Engineer to join one of our trading teams. We’re seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design.
- Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up
- Research and evaluate a variety of cutting-edge FPGA hardware and technologies
- Propose creative solutions to overcome FPGA/hardware limitations
- Liaise directly with software and other design teams
- Conduct lab debugging and characterization of new hardware
- Bachelor’s degree or higher, Computer/Electrical Engineering with 3+ years of experience within the field; (Master’s degree or higher also counts for experience)
- Solid Hardware Engineering experience, especially with FPGA
- Highly autonomous with a can-do attitude able to lead an FPGA based project from system requirements to production
- Strong capacity to quickly evaluate FPGA based project feasibility based on hardware limitation
- Strong skills in RTL logic design (Verilog) and verification; 2+ years of experience writing Verilog
- Experience in FPGA design flow including synthesis, place & route , static timing analysis is required
- Experience with the design of system-on-chip (SOC) architectures, memory & processor subsystems, networking, and peripheral interconnect is required
- Knowledge of the TCP/IP stack
- Strong working knowledge of either XILINX or ALTERA FPGA design flow
- Experience with functional verification utilizing high-level methodologies (e.g. System Verilog) is a plus.
- Excellent research and data gathering skills
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