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FPGA Verification Engineer (JAX)

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Job Location
Chicago
Employment Type
Regular
Department
Technology
Targeted Start Date
Immediate

DRW is a technology-driven, diversified principal trading firm. We trade our own capital at our own risk, across a broad range of asset classes, instruments and strategies, in financial markets around the world. As the markets have evolved over the past 25 years, so has DRW – maximizing opportunities to include real estate, cryptoassets and venture capital. With over 1000 employees at our Chicago headquarters and offices around the world, we work together to solve complex problems, challenge consensus and deliver meaningful results. It’s a place of high expectations, deep curiosity and thoughtful collaboration.

DRW is looking for an outstanding Verification Engineer to join a team of highly talented Engineers tasked with building a cutting edge, low latency trading application.  In this role, you will have the opportunity collaborate with other Engineers, Traders, and Researchers around the globe to in order to build and expand upon DRW’s trading platform’s capabilities.

You’ll be working on:

  • All aspects of individual block-level and full project level verification including framework/environment development, test plan development and execution, code/functional coverage closure and reviews
  • Building out RTL and software co-simulation environments
  • Creating new tests for new and existing designs and integrating into the current continuous integration (CI) framework
  • Supporting regression runs
  • Building and maintaining tools and processes associated with FPGA verification.
  • Collaborating with a team of FPGA Designers on FPGA project verification.

You'll feel right at home if you:

  • Are proficient in coding with SystemVerilog and Python
  • Have a minimum of 2 years of relevant experience in ASIC/FPGA Verification
  • Have experience with Python for high level stimulus generation and model development
  • Have experience with Linux and networking protocol (Ethernet among others)
  • Are familiar with functional coverage and code coverage
  • Possess excellent written and oral communication skills (for MTL: in English,) including the ability to produce clear, concise documentation
  • Enjoy working in a fast-paced, multi-project team environment

Bonus points if you have experience with:

  • C/C++ and DPI interface to simulators
  • Hardware integration testing
  • Production system support and troubleshooting
  • Modelsim and Questa experience

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California residents, please review the California Privacy Notice for information about certain legal rights at https://drw.com/california-privacy-notice.

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