background image

FPGA Engineer (Trading Team)

View all jobs
Job Location
Chicago
Employment Type
Regular
Department
Technology
Targeted Start Date
Immediate

DRW is a technology-driven, diversified principal trading firm. We trade our own capital at our own risk, across a broad range of asset classes, instruments and strategies, in financial markets around the world. As the markets have evolved over the past 25 years, so has DRW – maximizing opportunities to include real estate, cryptoassets and venture capital. With over 1000 employees at our Chicago headquarters and offices around the world, we work together to solve complex problems, challenge consensus and deliver meaningful results. It’s a place of high expectations, deep curiosity and thoughtful collaboration.

We are currently seeking an FPGA Engineer to join one of our trading teams. We’re seeking a candidate that has a strong understanding of software and hardware interaction.  This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design.  This role can sit in Chicago where the trading is based, or remotely in the US or Canada.

Responsibilities: 

  • Architect, implement and maintain FPGA applications (synthesis, place & route, static timing analysis, documentation)
  • Research and evaluate a variety of cutting-edge FPGA hardware and technologies
  • Propose creative solutions to overcome FPGA/hardware limitations
  • Liaise directly with software, networking, and trading teams
  • Conduct lab debugging and characterization of new hardware

Candidate Requirements: 

  • Bachelor’s degree or higher, Computer/Electrical Engineering with 3+ years of experience within the field; (Master’s degree or higher also counts for experience)
  • Solid Hardware Engineering experience, especially with FPGA
  • Strong capacity to quickly evaluate FPGA based project feasibility based on hardware limitation
  • Strong skills in RTL logic design (Verilog) and verification; 2+ years of experience writing Verilog
  • Experience in FPGA design flow including synthesis, place & route, static timing analysis is required
  • Knowledge of I/O protocols (TCP/IP, UDP, Ethernet, PCIe, etc)
  • Strong working knowledge of either XILINX or ALTERA FPGA design flow
  • Experience with functional verification utilizing high-level methodologies (e.g. System Verilog) is a plus.
  • Experience working with software programming languages is a plus (C++, Python, etc.)
  • Excellent research and data gathering skills

For more information about DRW's processing activities and our use of job applicants' data, please view our Privacy Notice at https://drw.com/privacy-notice.

California residents, please review the California Privacy Notice for information about certain legal rights at https://drw.com/california-privacy-notice.

LI-BL1